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Flow control, QoS loom large in RapidIO 2.0
Asia-based hardware developers who got an early peek at the next spin of Serial RapidIO seemed as interested in flow control and quality-of-service mechanisms as they were in the speed improvement to 6.125 Gbits/second. Tom Cox, executive director of the RapidIO Trade Association, said this indicates that SRIO is moving beyond a single line or switch card to backplane and even box-to-box interconnect in telecom equipment design. Details... more »
Asia-based hardware developers who got an early peek at the next spin of Serial RapidIO seemed as interested in flow control and quality-of-service mechanisms as they were in the speed improvement to 6.125 Gbits/second. Tom Cox, executive director of the RapidIO Trade Association, said this indicates that SRIO is moving beyond a single line or switch card to backplane and even box-to-box interconnect in telecom equipment design. Details... more »
Systems-on-chip: Library bolsters SystemC
Filling what it sees as missing capabilities in the SystemC verification environment, Jeda Technologies Inc. this week will introduce NSCv, a C++ verification class library for SystemC. Details... more »
Filling what it sees as missing capabilities in the SystemC verification environment, Jeda Technologies Inc. this week will introduce NSCv, a C++ verification class library for SystemC. Details... more »
SysVerilog support falls short for design
A full-court marketing push by major EDA vendors on behalf of the SystemVerilog language is working--but not as expected. Although the unified design and verification language is widely applied to verification, design use lags because of concerns about tool support.</P> Details... more »
A full-court marketing push by major EDA vendors on behalf of the SystemVerilog language is working--but not as expected. Although the unified design and verification language is widely applied to verification, design use lags because of concerns about tool support.</P> Details... more »