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Clocks and Timers CDCLVD110A 1-to-10 LVDS Clock Buffer up to 900MHz with Minimum Skew for Clock Distribution

Clocks and Timers CDCLVD110A 1-to-10 LVDS Clock Buffer up to 900MHz with Minimum Skew for Clock Distribution
The CDCLVD110A clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0-Q9) with minimum skew for clock distribution. The CDCLVD110A is specifically designed to drive 50- transmission lines. When the control enable is high (EN = 1), the 10 differential...
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2007-02-18 16:30:25
 
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